|
|
SpaceWire Endpoint verification
Peroutka, Ondřej ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The topic of the bachelor´s thesis is the verification of the SpaceWire endpoint IP core created at Department of Microelectronics, Faculty of Electrical Engineering and Communication, VUT Brno. The thesis has 3 major parts. The first part briefly describes the SpaceWire standard. The second part deals with the theoretical description of the verification. The last part deals with the verification of the SpaceWire endpoint.
|
|
|
Industrial digital cameras
Palát, David ; Kovář, Jiří (referee) ; Houška, Pavel (advisor)
This reasearch introduces reader of base parts of digital camera. This body of work investigates functions and characteristics of these parts. Shows benefits and handicaps concrete technologies. The main koncept is to achieve a full comparison of the different kinds of used technologies.
|
|
|
Implementation of fast serial bus on FPGA
Drbal, Jakub ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
This diploma thesis deals with implementation of fast serial bus and SATA controler in the FPGA chip. The work is divided into two parts. In the first part the circuit for communication between the FPGAs is designed and in the second part the circuit for direct connection of SATA hard disk to a gate array is created. The circuit for communication between the FPGA is designed according to SATA specification. Link layer and physical layers are implemented in VHDL with programmable logic resources.
|
|
|
Development of high resolution RGB camera
Madeja, Jiří ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
Tato práce se zabývá výběrem vhodného obrazového snímače pro použití v kameře snímající rostliny ve vysokém rozlišení a návrhem vhodného obvodu pro propojení vybraného snímače (SONY IMX253) s vývojovou deskou Avnet MicroZed. Tato práce pojednává o jednotlivých parametrech obrazových snímačů podle kterých je vybírán vhodný obrazový snímač. Je vysvětlen proces výběru vhodného obrazového snímače a podrobněji popsány parametry vybraného snímače. Je naznačena problematika návrhu elektroniky a plošných spojů z hlediska požadavků vysokorychlostních obvodů a citlivých a specifických součástek jako je obrazový snímač. Je nastíněna konfigurace a programování obvodu Xilinx Zynq a nakonec je provedeno zjednodušené teoretické ověření funkčnosti navrženého modulu.
|
|
|
Multichannel HD-SDI digital video signal converter
Kučera, Stanislav ; Bobula, Marek (referee) ; Kubíček, Michal (advisor)
This master’s thesis deals with the design of six channel SD, HD and 3G HD-SDI digital video signal converter to 10-Gigabit Ethernet. In the introductory part, the conception of designed device is formulated. The theoretical background is provided in four chapters, where main standards and design rules related to digital electronics’ design are analyzed. The emphasis is placed on signal integrity at high-speed interconnects. There mostly practical examples, calculations and simulations are utilized. The design part contains thorough description of main subsystems’ design, implementation of FPGA, SDI input channels and 10-Gigabit Ethernet PHY. In the final part, the first tests and measurements of the build prototype are summarized. As an example, the comparison of signal integrity simulation to measurement is provided.
|
|
|
Design of the LVDS bus with hight EMC immunity
Klauda, Zbyněk ; Fiala, Pavel (referee) ; Kroutilová, Eva (advisor)
My thesis deals with project of LVDS busbar with high resistivity with regard to disturbance from surroundings and radiation undesirable electromagnetic waves into its environment. Project of LVDS busbar was elaborated by numeric methods and it was suggested optimal solution of the shape and material of multiply technology DPS. The project was realized on desired driving-point impenance of busbar Z=100 ohm with frequency f1=100 MHz of the first harmonic component rectangular signal of defind modality, entering and diagonal edge.
|
|
|
Design of multipurpose generator of low- and high-frequency sub-bands
Caban, Dominik ; Brančík, Lubomír (referee) ; Šotner, Roman (advisor)
The thesis focuses on the generation of harmonic and non-harmonic waveforms in the low and high-frequency domains. The thesis aims to design and implement a portable multipurpose signal generator with a user interface powered by its own battery. The design focuses on the implementation of a function generator, a high-frequency generator, and a pulse generator with Gaussian characteristics within a single portable device. The thesis describes an introduction to signal generators, the selection of the individual components, the design procedure for each circuit, and their subsequent hardware implementation either within the development kit or the final product.
|
|
|
Development of high resolution RGB camera
Madeja, Jiří ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
Tato práce se zabývá výběrem vhodného obrazového snímače pro použití v kameře snímající rostliny ve vysokém rozlišení a návrhem vhodného obvodu pro propojení vybraného snímače (SONY IMX253) s vývojovou deskou Avnet MicroZed. Tato práce pojednává o jednotlivých parametrech obrazových snímačů podle kterých je vybírán vhodný obrazový snímač. Je vysvětlen proces výběru vhodného obrazového snímače a podrobněji popsány parametry vybraného snímače. Je naznačena problematika návrhu elektroniky a plošných spojů z hlediska požadavků vysokorychlostních obvodů a citlivých a specifických součástek jako je obrazový snímač. Je nastíněna konfigurace a programování obvodu Xilinx Zynq a nakonec je provedeno zjednodušené teoretické ověření funkčnosti navrženého modulu.
|
|
|
SpaceWire Endpoint verification
Peroutka, Ondřej ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The topic of the bachelor´s thesis is the verification of the SpaceWire endpoint IP core created at Department of Microelectronics, Faculty of Electrical Engineering and Communication, VUT Brno. The thesis has 3 major parts. The first part briefly describes the SpaceWire standard. The second part deals with the theoretical description of the verification. The last part deals with the verification of the SpaceWire endpoint.
|
|
|
Implementation of fast serial bus on FPGA
Drbal, Jakub ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
This diploma thesis deals with implementation of fast serial bus and SATA controler in the FPGA chip. The work is divided into two parts. In the first part the circuit for communication between the FPGAs is designed and in the second part the circuit for direct connection of SATA hard disk to a gate array is created. The circuit for communication between the FPGA is designed according to SATA specification. Link layer and physical layers are implemented in VHDL with programmable logic resources.
|
guest ::
